A PLL (Phase Locked Loop) is commonly used for communication, multimedia, and other applications. FIG. 1 is a block diagram illustrating a conventional charge pump PLL (Phase Locked Loop). An input clock 101 is inputted to a pre-divider 110 and the pre-divider 110 converts the input clock 101 to a lower frequency clock 111. The converted lower frequency clock 111 is provided to a phase frequency detector (PFD) 120. The phase frequency detector 120 compares a phase of the lower frequency clock 111 to a phase of a final clock 161 generated from a main-divider 160 and outputs an UP signal 121 and/or a DOWN signal 122. When the phase of the lower frequency clock 111 leads the phase of the final clock 161, the UP 121 signal is activated and the DOWN signal 122 is inactivated. Conversely, when the phase of the lower frequency clock 111 lags behind the phase of the final clock 161, the DOWN signal 122 is activated and the UP signal 121 is inactivated.
A charge pump 130 outputs a current (Icp) 131 to a loop filter 140 when the UP signal 121 is activated and pulls the current (Icp) 131 from the loop filter 140 when the DOWN signal 122 is activated. An output voltage 141 of the loop filter 140 increases when the phase frequency detector 120 outputs the UP signal 121 having an active state, and the output voltage 141 of the loop filter 140 decreases when the phase frequency detector 120 outputs the DOWN signal 122 having an active state. The loop filter 140 is illustrated as containing a resistor R and capacitors C1 and C2.
The output voltage 141 of the loop filter 140 is provided to a voltage-controlled oscillator (VCO) 150 and is used for controlling a frequency of an output clock 151. This output clock 151 may be the same signal as FOUT. The frequency of the output clock 151 outputted from the VCO 150 is generally proportional to an input voltage of the VCO 150 (i.e., the output voltage 141 of the loop filter 140). The output clock 151 of the VCO 150 is divided by the main-divider 160 and the divided output clock 161 is fed back to the phase frequency detector 120. The main-divider 160 may be optionally included in the charge pump PLL. In particular, the output clock 151 of the VCO 150 is divided by the main-divider 160 and the divided output clock 161 is provided to the phase frequency detector 120 when the PLL performs a function of frequency multiplication. In addition, the main-divider 160 and the pre-divider 110 can determine a frequency ratio of the output clock 161 to the input clock 101.
An important factor in defining the performance of the PLL is a ‘locking time’ that represents a time required for generating an output clock synchronized to an input clock and having a predetermined target frequency. Communication, multimedia, and other applications utilizing the PLL require a fast locking time.
Referring to the charge pump PLL shown in FIG. 1, the locking time may be re-defined as a time required for a control voltage 141 of the VCO 150 to reach a voltage level that is required to generate the predetermined target frequency. According to the conventional charge pump PLL shown in FIG. 1, the magnitude of the current (Icp) 131 outputted from the charge pump 130 during an initial stage of a phase lock operation is equal to the magnitude of the current (Icp) 131 outputted from the charge pump 130 during a stage in which the phase lock is almost completed. The locking time of the PLL is substantially inversely proportional to the quantity of the current (Icp) 131 outputted from the charge pump 130. However, when the quantity of the current (Icp) 131 outputted from the charge pump 130 is increased in order to reduce the locking time of the charge pump PLL, spectral purity (or reliability) of the PLL is degraded and noise of the output clock increases. That is, in a PLL employing single charge pump, there is often a trade-off between fast locking time and good reliability.
In order to solve these problems, a structure of a modified PLL is disclosed in Japan Patent No. 98376. The PLL of the Japan Patent No. 98376 includes a plurality of charge pump units and the PLL operates in two modes, i.e. a high-speed mode in which the charge pump units provide a large current and a low noise mode.
However, the PLL of the Japan Patent No. 98376 controls the switching between the two modes of the charge pump unit, which provides a large current in the high-speed mode, using a logic circuit. The PLL can't variably control the quantity of the current outputted from a charge pump based on a phase difference between an input clock and an output clock. Additionally, jitter of the output clock may be generated since a switching noise due to a switching of the charge pump unit for performing the high-speed mode is applied to a loop filter.
Another conventional charge pump PLL is disclosed in U.S. Pat. No. 5,424,689, which is entitled “Filtering device for use in a phase locked loop controller”. The charge pump PLL of U.S. Pat. No. 5,424,689 includes two-type charge pumps, including of a high current charge pump for providing a large current and a small current charge pump for providing a small current. However, the current transfer of two charge pumps are controlled using a variable transmission characteristic of a loop filter based on a fact that the transmission characteristics of the loop filter depend upon connect points between each of the two charge pumps and the loop filter.